The invention relates to an integrated DRAM memory component having sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures which comprise amplification transistors for bit line signal amplification, which are of identical design and are opposite one another in pairs in adjacent transistor rows, and signal interconnects, which are associated with the transistor rows and run parallel thereto, for supplying actuation signals.
In such an integrated memory component, the bit line signal is typically amplified by four amplification transistors. The sense amplifiers respectively adjacent to four amplifier transistors are arranged next to one another in the layout in a row or in the form of a strip and thus form a regular structure. In particular these transistors are respectively arranged in pairs opposite one another in the rows, are of identical design and are arranged at an equal distance from one another in the row or in the strip. On account of the very small dimensions of the respective sense amplifier, this regular structure is a necessary prerequisite for the exact mapping of a predetermined geometry on a wafer.
A problem with the current integrated DRAM memory component of the above-mentioned type is that the asymmetrical arrangement of the signal interconnects for supplying actuation signals to the transistor structures means that different capacitive coupling of these signals into the amplification transistors can result in the response of the memory component""s sense amplifier becoming asymmetrical, particularly in the case of small bit line signals. A consequence of this is that weak memory cells are not read correctly, which ultimately affects the yield, because signal reserve is lost on account of the asymmetrical response of the sense amplifiers, which also manifests itself in a correspondingly impaired signal-to-noise ratio.
U.S. Pat. No. 4,402,063 discloses an integrated memory component of the generic type. Similar memory component layouts are described in U.S. Pat. No. 4,634,901 and U.S. Pat. No. 4,747,078.
It is accordingly an object of the invention to provide an integrated DRAM memory component, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which ensures that the response of the sense amplifiers is symmetrical even in the case of small bit line signals.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated DRAM memory component, comprising:
sense amplifiers each formed from mutually adjacent transistor rows and having amplification transistors for bit line signal amplification and signal interconnects for supplying actuation signals to said amplification transistors;
said amplification transistors being structurally identical and being disposed opposite one another in pairs in adjacent transistor rows of said sense amplifiers;
said signal interconnects associated with said sense amplifiers running parallel to said transistor rows, said signal interconnects for supplying the actuation signals to said amplification transistors having a substantially identical arrangement symmetry relative to said transistor rows as said amplification transistors, such that said amplification transistors in adjacent said transistor rows are disposed in a same interconnect proximity with regard to said signal interconnects for supplying the actuation signals to said amplification transistors;
said signal interconnects including a first signal interconnect for a first actuation signal and a second signal interconnect for a second actuation signal, said first signal interconnect running centrally between two said transistor rows, and said second signal interconnect being split into two parallel signal interconnect sections running symmetrically on both sides of said first signal interconnect;
a signal supply interconnect for supplying said first signal interconnect with the first actuation signal, said signal supply interconnect running transversely with respect to said first signal interconnect on one side of said first signal interconnect in a region of one said transistor row; and
a dummy signal supply interconnect identical to said signal supply interconnect and running transversely with respect to said first signal interconnect on another side of said first signal interconnect in a region of the other transistor row, such that said amplification transistors in said adjacent transistor rows are formed in a same signal supply interconnect proximity.
Accordingly, the invention provides a fully symmetrical signal interconnect in proximity for the amplification transistors in adjacent transistor rows. In other words, each amplification transistor xe2x80x9cseesxe2x80x9d the same signal interconnect environment, which means that the sense amplifiers comprising these transistors have a symmetrical response even when small bit line signals are applied.
The underlying concept behind the invention can also be understood to be that the highly symmetrical transistor structures, which are distributed over transistor rows running parallel to one another, have correspondingly highly symmetrical signal interconnect structures associated with them whose symmetry corresponds to the symmetry of the amplification transistor structures. In contrast to this, the prior art provides a highly symmetrical arrangement of the transistor structures, but no highly symmetrical arrangement which correlates thereto, rather an asymmetrical arrangement of the signal interconnect structures in association with the transistor structures, which is why the DRAM memory component based on the prior art results in an asymmetrical response from the sense amplifiers when small bit line signals are applied.
The inventive concept is realized for the integrated DRAM memory component in question, which has a first signal interconnect for a first actuation signal and a second signal interconnect for a second actuation signal, by virtue of the first signal interconnect running between two transistor rows, while the second signal interconnect is split into two parallel signal interconnects which run symmetrically on both sides of the first signal line.
The general inventive concept can be applied not just to symmetrical proximity for all the amplification transistors not just in relation to the signal inter-connects, but also to signal supply interconnects for supplying the signal interconnects with an actuation signal, the respective signal supply interconnect running transversely with respect to the respective signal interconnect on one side of the latter in the region of a transistor row. In the case of such a signal interconnect/signal supply interconnect structure, the invention provides for a dummy signal supply interconnect, which is identical to the signal supply interconnect, to be arranged in the region of the opposite transistor row such that the amplification transistors in the adjacent transistor rows are in the same signal supply interconnect proximity. Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated DRAM memory component, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.